IEEE VLSI Test Symposium 2023
The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems.
Join us at VLSI Test Symposium event and meet Sylvain Guilley, CTO of Secure-IC during a dedicated speech:
ABSTRACT:
- Secure chips implement cryptographic algorithms and protocols to ensure self-protection (e.g., firmware authenticity) as well as user data protection (e.g., encrypted data storage).
In turn, cryptography needs to defer to incorruptible sources of entropy to implement their functions according to their mandatory usage guidance.
Typically, keys, nonces, initialization vectors, etc. shall not be guessed by attackers.
In practice, True Random Number Generators (TRNGs) are in charge of producing such sensitive elements.
Fully aware of the central role of TRNGs in the security correct implementation in chips, stakeholders have been formalizing requirements recently.
The methods to strengthen requirements are manifold.
In this session, we discuss and apply three of them by targeting the Set-Reset Latch TRNG which is an alternative to Ring-Oscillator (RO) TRNGs as it provides faster throughputs.
The first method concerns the confidence in the TRNG being random enough.
It explores how the TRNG properties can be reliably predicted by simulation, compared to real silicon experiments.
The second aspect dealt with in this session is the assessment of the TRNG properties across aging.
Such knowledge is important as secure chips are expected to be in service for a long period, and it would be detrimental to the service they render if the quality of the entropy they deliver would be declining over time.
Eventually, the third aspect of this session is the timely detection of unforeseen failures or malevolent attacks.
The mitigation lies in leveraging “health tests” launched prior to using random numbers.
Practical details:
- 📅 Monday, April 24
- 🕔 12:00 pm